? semiconductor components industries, llc, 2012 march, 2012 ? rev. 1 1 publication order number: ncp81081/d ncp81081 integrated driver and mosfet the ncp81081 integrates a mosfet driver, high ? side mosfet and low ? side mosfet into a 6 mm x 6 mm 40 ? pin qfn package. the driver and mosfets have been optimized for high ? current dc ? dc buck power conversion applications. the ncp81081 integrated solution greatly reduces package parasitics and board space compared to a discrete component solution. features ? capable of switching frequencies up to 1 mhz ? capable of output currents up to 35 a ? pwm input capable of 3.3 v and 5 v ? internal bootstrap diode ? zero current detection ? undervoltage lockout ? internal thermal warning / thermal shutdown ? these are pb ? free devices disb# pwm vcin boot vin vswh pgnd output disable pwm 5v vout cgnd 12 ? 20 v zcd_en# zcd enable thwn thermal warning figure 1. application schematic 5 v phase device package shipping ? ordering information qfn40 (pb ? free) 2500/tape & reel NCP81081MNR2G marking diagram qfn40 mn suffix case 485az http://onsemi.com ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. ncp81081 awlyywwg 1 a = assembly location wl = wafer lot yy = year ww = work week g = pb ? free package 40 1 qfn40 (pb ? free) 2500/tape & reel ncp81081mntwg
ncp81081 http://onsemi.com 2 pwm logic anti ? cross vcin vcin disb# uvlo thwn/thdn vswh vin pgnd boot gh gl zcd_en# thwn conduction figure 2. simplified block diagram phas e cgnd flag41 vin flag42 vswh flag43 40 31 32 33 34 35 36 37 38 39 11 20 19 18 17 16 15 14 13 12 pwm disb# cgnd thwn gl vswh vswh vswh vswh vswh vin vin vin vin vswh pgnd pgnd pgnd pgnd pgnd pgnd figure 3. pin connections (top view) pgnd pgnd pgnd pgnd pgnd pgnd pgnd vswh vswh vin vin nc phase gh cgnd boot nc vcin zcd_en# 21 22 23 24 25 26 27 28 29 30 10 9 8 7 6 5 4 3 2 1
ncp81081 http://onsemi.com 3 table 1. pin function description pin no. pin name description 1 zcd_en# enable zero current detection 2 vcin control input voltage 3, 8 nc no connect 4 boot bootstrap voltage 5, 37, flag 41 cgnd control signal ground 6 gh high side fet gate access 7 phase provides a return path for the high side driver of the internal ic. place a high frequency ceram- ic capacitor of 0.1 uf to 1.0 uf from this pin to boot pin. 9 ? 14, flag 42 vin input voltage 15, 29 ? 35, flag 43 vswh switch node output 16 ? 28 pgnd power ground 36 gl low side fet gate access 38 thwn thermal warning 39 disb# output disable pin 40 pwm pwm drive logic table 2. absolute maximum ratings pin symbol pin name min max vcin control input voltage ? 0.3 v 7 v vin power input voltage ? 0.3 v 30 v boot bootstrap voltage ? 0.3 v wrt/vswh 35 v wrt/pgnd 40 v < 50 ns wrt/pgnd 7 v wrt/vswh vswh switch node output ? 0.3 v 30 v zcd_en# zero current detection ? 0.3 v 6.5 v pwm pwm drive logic ? 0.3 v 6.5 v disb# output disable ? 0.3 v 6.5 v thwn thermal warning ? 0.3 v 6.5 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. table 3. thermal characteristics rating symbol value unit thermal resistance, high ? side fet r jpcb 13 c/w thermal resistance, low ? side fet r jpcb 5 c/w operating junction temperature t j 0 to 150 c storage temperature t s ? 55 to 150 c moisture sensitivity level msl 3 table 4. operating ranges rating symbol min typ max unit control input voltage vcin 4.5 5 5.5 v input voltage vin 4.5 12 25 v
ncp81081 http://onsemi.com 4 electrical characteristics (note 1) (vcin = 5 v, vin = 12 v, t a = ? 10 c to +100 c, unless otherwise noted) parameter symbol condition min typ max unit supply current vcin current (normal mode) ? disb# = 5 v, pwm = osc, fsw = 400 khz 14 20 ma vcin current (shutdown mode) ? disb# = gnd 15 30 a undervoltage lockout uvlo startup ? 3.8 4.35 4.5 v uvlo hysteresis ? 150 200 250 mv bootstrap diode forward voltage ? vcin = 5 v, forward bias current = 2 ma 0.1 0.4 0.6 v pwm input pwm input voltage high v pwm_hi 2.65 ? ? v pwm input voltage mid ? state v pwm_mid 1.4 ? 2.0 v pwm input voltage low v pwm_lo ? ? 0.7 v tri ? state shutdown holdoff time t holdoff 250 ns pwm input resistance 63 k pwm input bias voltage 1.7 v output disable output disable input voltage high v disb#_hi 2.0 ? ? v output disable input voltage low v disb#_lo ? ? 0.8 v output disable hysteresis ? ? 500 ? mv output disable propagation delay ? 20 40 ns zero cross detect zero cross detect high v zcd_en#_hi 2.0 ? ? v zero cross detect low v zcd_en#_lo ? ? 0.8 v zero cross detect threshold ? 6 mv zcd blanking timer 250 ns thermal warning/shutdown thermal warning temperature 150 c thermal warning hysteresis 15 c thermal shutdown temperature 180 c thermal shutdown hysteresis 25 c 1. performance guaranteed over the indicated operating temperature range by design and/or characterization tested at t j = t a = 25 c. low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
ncp81081 http://onsemi.com 5 applications information theory of operation the ncp81081 is an integrated driver and mosfet module designed for use in a synchronous buck converter topology. a single pwm input signal is all that is required to properly drive the high ? side and low ? side mosfets. low ? side driver the low ? side driver is designed to drive a ground ? referenced low r ds(on) n ? channel mosfet. the voltage rail for the low ? side driver is internally connected to vcin and pgnd. high ? side driver the high ? side driver is designed to drive a floating low rds(on) n ? channel mosfet. the gate voltage for the high side driver is developed by a bootstrap circuit referenced to switch node (vswh) pin. the bootstrap circuit is comprised of the internal diode and an external bootstrap capacitor. when the ncp81081 is starting up, the vswh pin is at ground, so the bootstrap capacitor will charge up to vcin through the bootstrap diode see figure 1. when the pwm input goes high, the high ? side driver will begin to turn on the high ? side mosfet using the stored charge of the bootstrap capacitor. as the high ? side mosfet turns on, the vswh pin will rise. when the high ? side mosfet is fully on, the switch node will be at 12 v, and the bst pin will be at 5 v plus the charge of the bootstrap capacitor (approaching 17 v). the bootstrap capacitor is recharged when the switch node goes low during the next cycle. zero current detect when zcd_en# is set high, the ncp81081 will operate in normal pwm mode. when zcd_en# is set low, zero current detect (zcd) will be enabled. if pwm goes high, gh will go high after the non ? overlap delay. if pwm goes low, gl will go high after the non ? overlap delay, and stay high for the duration of the zcd blanking timer. once this timer has expired, vswh will be monitored for zero current detection, and will pull gl low once detected. the threshold on vswh to determine zero current undergoes an auto-calibration cycle every time disb# is brought from low to high. this auto-calibration cycle typically takes 25 s to complete. safety timer and overlap protection circuit it is very important that mosfets in a synchronous buck regulator do not both conduct at the same time. excessive shoot ? through or cross conduction can damage the mosfets, and even a small amount of cross conduction will cause a decrease in the power conversion efficiency. the ncp81081 prevents cross conduction by monitoring the status of the mosfets and applying the appropriate amount of ?dead ? time? or the time between the turn off of one mosfet and the turn on of the other mosfet. when the pwm input pin goes high, the gate of the low ? side mosfet (gl pin) will go low after a propagation delay (tpdlgl). the time it takes for the low ? side mosfet to turn off (tfgl) is dependent on the total charge on the low ? side mosfet gate. the ncp81081 monitors the gate voltage of both mosfets and the switchnode voltage to determine the conduction status of the mosfets. once the low ? side mos fet is turned off an internal timer will delay (tpdhgh) the turn on of the high ? side mosfet. likewise, when the pwm input pin goes low, the gate of the high ? side mosfet (gh pin) will go low after the propagation delay (tpdlgh). the time to turn off the high ? side mosfet (tfgh) is dependent on the total gate charge of the high ? side mosfet. a timer will be triggered once the high ? side mosfet has stopped conducting, to delay (tpdhgl) the turn on of the low ? side mosfet. th ermal warning / thermal shutdown when the temperature of the driver reaches 150 c, the thwn pin will be pulled low indicating a thermal warning. at this point, the part continues to function normally. when the temperature drops below 135 c, the thwn will go high. if the driver temperature exceeds 180 c, the part will enter thermal shutdown and turn off both mosfets. once the temperature falls below 155 c, the part will resume normal operation. the thwn pin has a maximum current capability of 30 ma. power supply decoupling the ncp81081 can source and sink relatively large current to the gate pins of the mosfets. in order to maintain a constant and stable supply voltage (vcin) a low esr capacitor should be placed near the power and ground pins. a 1 f to 4.7 f multi layer ceramic capacitor (mlcc) is usually sufficient. bootstrap circuit the bootstrap circuit uses a charge storage capacitor (c bst ) and the internal diode. the bootstrap capacitor must have a voltage rating that is able to withstand twice the maximum supply voltage. a minimum 50 v rating is recommended. a bootstrap capacitance greater than 100 nf and a minimum 50 v rating is recommended. a good quality ceramic capacitor should be used.
ncp81081 http://onsemi.com 6 zcd_en# pwm il gl gh figure 4. zero current detection figure 5. tri ? state operation pwm gl gh t holdoff t holdoff t holdoff
ncp81081 http://onsemi.com 7 package dimensions qfn40 6x6, 0.5p mn suffix case 485az issue o seating 0.15 c (a3) a a1 b 1 40 2x 2x 40x l 40x bottom view top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c e a 0.10 b c 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimensions: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from terminal 4. coplanarity applies to the exposed pad as well as the terminals. 5. positional tolerance applies to all three exposed pads. dim min max millimeters a 0.80 1.00 a1 ??? 0.05 a3 0.20 ref b 0.18 0.30 d 6.00 bsc d2 2.30 2.50 e 6.00 bsc 4.50 e2 4.30 e 0.50 bsc l 0.30 0.50 k 0.20 ??? plane soldering footprint d3 1.40 1.60 2.10 e3 1.90 l1 ??? 0.15 note 4 e/2 e2 d2 note 3 e3 43x detail b l1 detail a l alternate constructions l 2.20 bsc d3 e3 g detail a a 0.10 b c note 5 k dimensions: millimeters 2.16 6.30 4.56 4.56 2.56 0.50 0.63 0.30 40x 40x pitch 2.16 6.30 1.66 pkg outline 1 g g on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncp81081/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
|
